1. Field of the Invention
This invention relates to high speed computing apparatus and more particularly to an arithmetic unit for a vector signal processor used for signal and image processing applications.
2. Prior Art
Signal processing algorithms operating with very large amounts of data require extremely high processing throughput. Some attempts have been made to design pipelined arithmetic units, mainly as special arithmetic components, or building blocks, like multipliers and special purpose ALUs. Only a few of these designs use a programmable processor architecture for signal and image processing that involve transform and filter operations.
Complex computations, which are common to digital signal processing, require wide dynamic range and high accuracy. Different techniques have been implemented to achieve these criteria, such as enlarged data word lengths (using 24 to 32 bits per word), block floating-point arithmetic, and floating-point arithmetic.